1. Field of the Invention
The present invention relates, in general, to a semiconductor package and method for fabricating the same and, more particularly, to a semiconductor package and method for fabricating the same that allows a plurality of semiconductor chips to be fixedly stacked in a single, thin package.
2. Description of the Prior Art
Currently, there is a tendency in which a plurality of semiconductor chips are packaged and mounted on the motherboard of an electronic device such as a PCS phone, a cellular phone or a notebook to perform various functions within a minimum time, and semiconductor packages in which semiconductor chips are packaged and the electronic devices on which the semiconductor packages are mounted are miniaturized. In the meantime, in order to allow a semiconductor package to be thinned, there has been fabricated a semiconductor package in which an opening is formed in a circuit board and a semiconductor is disposed in the opening.
With reference to FIG. 7, the construction of such a semiconductor package 100xe2x80x2 is described as follows.
As depicted in the drawing, reference numeral 20xe2x80x2 designates a circuit board 20xe2x80x2 that has an opening 27xe2x80x2. A semiconductor 2xe2x80x2 on the upper surface of which a plurality of input/output pads 4xe2x80x2 are formed is disposed in the opening 27xe2x80x2 of the circuit board 20xe2x80x2. The circuit board 20xe2x80x2 comprises a base resin layer 21xe2x80x2. A circuit pattern including a plurality of bond fingers 22xe2x80x2 and ball lands 23xe2x80x2 are formed on the upper surface of the base resin layer 21xe2x80x2. The surface of the circuit pattern is coated with a cover coat 24xe2x80x2 with the bond fingers 22xe2x80x2 and the ball lands 23xe2x80x2 being exposed upward out of the cover coat 24xe2x80x2. The input/output pad 4xe2x80x2 of the semiconductor chip 2xe2x80x2 is electrically connected to the bond fingers 22xe2x80x2 of the circuit board 20xe2x80x2 by means of connection means 30xe2x80x2. Additionally, an encapsulation 40xe2x80x2 is formed around the semiconductor chip 2xe2x80x2 and the connection means 30xe2x80x2 so as to protect them from the external environment. A plurality of conductive balls 50xe2x80x2 are respectively fusion-welded on the ball lands 23xe2x80x2 to allow the package to be easily mounted on a motherboard.
However, in the conventional semiconductor package 100xe2x80x2, since only a single semiconductor chip 2xe2x80x2 is disposed in the opening 27xe2x80x2, there is an inherent shortcoming in the high density, function and capacity of semiconductor package 100xe2x80x2.
Furthermore, in a case where the semiconductor chip 2xe2x80x2 disposed in the opening of the circuit board 20xe2x80x2 is a memory chip, such as a flash memory chip, SRAM chip or the like, since a plurality of semiconductor packages 100xe2x80x2 must be mounted on a motherboard (not shown), there occurs a problem in which the mounting density is limited.
Recently, there is an increased desire for a semiconductor in which an ASIC (application specific integrated circuit) semiconductor chip and a memory semiconductor chip are packaged together. However, the desire is not satisfied by the conventional semiconductor package.
In order to overcome the problem, there has been developed a stack type semiconductor package in which a plurality of semiconductors respectively having various functions are packaged into a single semiconductor package by stacking the semiconductor chips together. The construction of the stack type semiconductor package is depicted in FIGS. 8A and 8B. FIG. 8A is a cross section of the package. FIG. 8B is a plan view showing the package in a state where the package is not coated with an encapsulation.
In the conventional stack type semiconductor package, a circuit board 10 on which bond fingers 12 are formed includes a resin layer 11, circuit patterns 19 are formed on the upper and lower surfaces of the resin layer 11, and a first semiconductor chip 1 is bonded on the center portion of the circuit board 10 with a bonding layer 7 interposed between the circuit board 10 and the first semiconductor chip 1. Reference numeral 14 designates conductive via holes for connecting the upper circuit pattern 18 to the lower circuit pattern 18, and reference numeral 15 designates cover coats for protecting the circuit patterns 19 from the external environment.
In addition, a second semiconductor chip 2 is bonded on the upper surface of the first semiconductor chip 1 with a bonding layer 7 interposed between the first and second semiconductor chip 1 and 2. The input/output pads 4A of the first semiconductor chip 1 and the input/output pads 4A of the second semiconductor chip 2 are formed along rectangular directions to prevent them from being overlapped. That is, as illustrated in FIG. 8B, the input/output pads 4A of the first semiconductor chip 1 and the input/output pads 4A of the second semiconductor chip 2 are prevented from being overlapped, in such a way that the input/output pads 4A of the first semiconductor chip 1 are arranged along the front and rear edges of the first semiconductor chip 1 and the input/output pads 4A of the second semiconductor chip 2 are arranged along the side edges of the second semiconductor chip 2. The input/output pads 4A of the first semiconductor chip 1 and the second semiconductor chip 2 are respectively connected to the bond fingers 12 of the circuit board 10 by means of connection means 20, such as conductive wires. A plurality of conductive balls 40 are respectively fusion-welded on a plurality of ball lands 13, which are formed on the lower surface of the circuit board 10, to transmit signals to a mother board. In the meantime, the first semiconductor chip 1, the second semiconductor chip 2 and the connection means 20 are encapsulated with an encapsulation 30 to protect them from the external environment.
However, in the conventional stack type semiconductor package 101xe2x80x2, the first semiconductor chip is bonded on the circuit board and the second semiconductor chip is bonded on the first semiconductor chip. Accordingly, the package is very thick which is contrary to recent trends.
Additionally, since the height difference between the input/output pads and the circuit board is excessively enlarged, the loop height of the connection means, such as conductive wires that connect the second semiconductor chip to the circuit pattern, tends to be enlarged. Accordingly, since the loop angle becomes an acute angle, the sweeping phenomenon of the conductive wires occurs easily by the filling pressure during a molding process, thereby causing the inferiority of the package.
As another example of the conventional semiconductor package, a composite stack type semiconductor package 102xe2x80x2 is illustrated in FIG. 9.
As depicted in the drawing, the conventional composite stack type semiconductor package is fabricated by stacking a plurality of conventional Ball Grid Array (BGA) semiconductor packages.
In each of the BGA semiconductor packages, a semiconductor chip 1 is positioned in the opening of a circuit board 10 on the upper and lower surfaces of which ball lands 13 are formed, the input/output pads (not shown) of the semiconductor chip 1 are respectively connected to the bond fingers 12 of conductive material formed on the upper surface of the circuit board 10 by conductive wires 20, the ball lands 13 are electrically connected to the bond fingers 12 through conductive via holes 14, conductive balls 40 are fusion-welded on the ball lands 13, and an encapsulation 30 is formed on the upper surface of the circuit board 10 to protect the semiconductor chip 1 and the conductive wires 20 from the external environment. In this case, the bond fingers 12 formed on the upper surface of the circuit board 10 are exposed to the outside, and projected pads 8 are respectively formed on the bond fingers 12.
In this conventional BGA package, since the semiconductor chip is disposed in the opening in the central portion of the circuit board, the semiconductor package can be fabricated to be relatively thin. Additionally, a plurality of BGA packages are stacked in such a way that one BGA package is bonded on another BGA package with the solder balls on the lower surface of the upper BGA being fusion-welded on the projected pads on the upper surface of the lower BGA, thereby increasing the mounting density of the package.
However, in the conventional composite stack type semiconductor package 102xe2x80x2, since projected pads are formed on the periphery of the circuit board of the BGA package 103xe2x80x2 and solder balls are fusion-welded on the projected pads, the semiconductor package causes inconvenience in having an extra step to form the projected pads, and has a limitation on the reduction of the thickness of electronic devices owing to the thickness of the projected pads. Additionally, in each of BGA packages, since a single chip is mounted in each package, there occur limitations on the maximization of the memory capacity of each package and the increase of the mounting density of each package.
Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and a first object of the present invention is to provide a semiconductor package in which at least two semiconductor chips are mounted at the position of the opening of a circuit board, thereby allowing the semiconductor package to be thinned and achieving high mounting density, high function and high capacity.
A second object of the present invention is to provide a semiconductor package in which solder ball lands are formed on the upper and lower surfaces of its circuit board and a plurality of sub-semiconductor packages are stacked using the solder ball lands, thereby allowing the semiconductor package to be thinned still more and maximizing mounting density and memory capacity.
A third object of the present invention is to provide a method for fabricating a semiconductor package in accordance with the first object, which is capable of eliminating a wire sweeping phenomenon.
In one embodiment of the invention, there is provided a semiconductor package, comprising: a circuit board having, a resin layer provided with an opening at its center portion, and a circuit pattern formed on at least one of the upper and lower surfaces of the resin layer, the circuit pattern including one or more bond fingers and ball lands exposed to the outside; at least two semiconductor chips on one surface of each of which a plurality of input/output pads are formed, the semiconductor chips being stacked at a position of the opening of the circuit board; electric connection means respectively connecting the input/output pads of the semiconductor chips to the bond fingers of the circuit board; an encapsulation with which the semiconductor chips are encapsulated so as to protect them from the external environment; and a plurality of conductive balls fusion-bonded on the ball lands of the circuit board; wherein at least one of the semiconductor chips exists within the opening of the circuit board.
In accordance with another embodiment of the invention, there is provided a semiconductor package, comprising: a first semiconductor chip on one surface of which a plurality of input/output pads are formed; a second semiconductor chip bonded by means of a bonding agent on one surface of the first semiconductor on which the input/output pads are formed; a circuit board having, a resin layer provided with an opening at its center portion, the opening being of a size for accommodating the first and second semiconductor chips, two circuit patterns formed on at least one of the upper and lower surfaces of the resin layer, and at least one cover coat with which the circuit pattern is coated; electric connection means respectively connecting the input/output pads of the first and second semiconductor chips to the bond fingers of the circuit board; an encapsulation with which the first and second semiconductor chips are encapsulated so as to protect them from the external environment; and a plurality of conductive balls fusion-bonded on the ball lands of the circuit board.
In various embodiments, one or both of the first and second semiconductor chips are rectangular in plan view, and the input/output pads of the first semiconductor chip and the input/output pads of the second semiconductor chip are respectively arranged along different directions in their sectional view or plan view.
In one embodiment, the first semiconductor chip is exposed out of the encapsulation at a surface opposite to a surface on which the second semiconductor chip is bonded.
In one embodiment, the input/output pads of the first and second semiconductor chips are arranged in directions opposite to those in which the conductive balls are arranged. Alternatively, the input/output pads of the first and second semiconductor chips are arranged in same directions as those in which the conductive balls are arranged.
The circuit board in one embodiment is fabricated in such a way that circuit patterns are formed on the upper and lower surfaces of the resin layer and the circuit patterns are electrically connected to each other through conductive via holes.
In accordance with another embodiment of the present invention, there is provided a semiconductor package, comprising: a circuit board having, a resin layer provided with an opening at its center portion, and two circuit patterns formed on the upper and lower surfaces of the resin layer, the circuit patterns including a plurality of bond fingers and ball lands exposed to the outside, wherein the circuit patterns are connected to each other through one or more via holes; a first semiconductor chip on a lower surface of which a plurality of input/output pads are formed, the first semiconductor chip being disposed in the opening of the circuit board; a second semiconductor chip on the upper surface of which a plurality of input/output pads are formed, the second semiconductor chip being bonded on the upper surface of the first semiconductor chip; connection means connecting the input/output pads of the first and second semiconductor chips to the bond fingers formed on the upper and lower surfaces of the circuit board; a first encapsulation with which a predetermined area of the lower surface of the circuit board covering the first semiconductor chip and the opening is encapsulated; a second encapsulation with which a predetermined area of the upper surface of the circuit board covering the second semiconductor chip and the opening is encapsulated; and a plurality of conductive balls fusion-bonded on the ball lands of the circuit board.
The package may further include a third semiconductor, the third semiconductor being connected to the bond fingers of the circuit board with connection means.
The package may further include a fourth semiconductor chip bonded on the lower surface of the first semiconductor chip, and connection means connecting the fourth semiconductor chip to the bond fingers of the circuit board.
The first encapsulation may be formed of a liquid phase encapsulation material and the second encapsulation may be formed of an epoxy molding compound.
The package may further include a dam formed along the upper surface of the circuit board in the vicinity of the opening so as to prevent a bonding agent for bonding the second semiconductor chip on the first semiconductor chip from overflowing.
In accordance with an embodiment of the present invention for accomplishing the second object, there is provided a semiconductor package, comprising: a semiconductor chip within an opening of a circuit board on the upper and lower surfaces of which two circuit patterns are respectively formed, the lower surface of the semiconductor chip and the lower surface of the circuit pattern formed the lower surface of the circuit board being on a same plane; electric connection means respectively connecting the input/output pads of the semiconductor chips to the circuit pattern formed on the upper surface of the circuit board; a plurality of conductive via holes electrically connecting the circuit patterns formed on the upper and lower surfaces of the circuit board to each other; a plurality of ball lands on which a plurality of conductive balls are fusion-bonded, the ball lands being formed on the circuit patterns formed on the upper and lower surfaces of the circuit board; and an encapsulation for protecting the semiconductor chip and the connection means from the external environment.
The the semiconductor chip may consist of at least two stacked sub-semiconductor chips, input/output pads of the sub-semiconductor chips being electrically connected to the circuit pattern formed on the upper surface of the circuit board by the connection means.
The semiconductor package may further include one or more additional semiconductor packages wherein a plurality of solder balls are fusion-bonded on the ball lands formed on the lower surface of the circuit board of each semiconductor package, all the semiconductor packages being fixedly stacked together with the solder balls of the lower surface of the circuit board of one semiconductor package being fusion-bonded on the ball lands of the upper surface of the circuit board of another semiconductor package.
In accordance with an embodiment of the present invention, there is provided a method for fabricating a semiconductor package, comprising: providing a circuit board, the circuit board having a resin layer and two circuit patterns, the resin layer being provided with an opening at its center portion, the circuit patterns being formed on the upper and lower surfaces of the resin layer and including a plurality of bond fingers and ball lands exposed to the outside, wherein the circuit patterns are connected to each other through one or more via holes; disposing a first semiconductor chip, on the lower surface of which a plurality of input/output pads are formed, in the opening of the circuit board, and connecting the input/output pads of the first semiconductor chip to the bond fingers of the circuit board with connection means; primarily encapsulating a predetermined area of the lower surface of the circuit board covering the first semiconductor chip and the opening with an encapsulating material; bonding a second semiconductor chip, on the upper surface of which a plurality of input/output pads are formed, on the upper surface of the first semiconductor chip, and connecting the input/output pads of the second semiconductor chip to the bond fingers of the circuit board with connection means; secondly encapsulating a predetermined area of the upper surface of the circuit board covering the second semiconductor chip and the opening with an encapsulating material; and fusion-bonding a plurality of conductive balls on the ball lands of the circuit board.
The first semiconductor chip may consist of at least two sub-semiconductors, i.e., two chips stacked upon each other.
The second semiconductor chip also may consist of at least two sub-semiconductors.
The method may further include the step of bonding another semiconductor chip on the lower surface of the first semiconductor chip after the step of disposing the first semiconductor within the opening of the circuit board.
The method may further include the step of bonding another semiconductor chip on the upper surface of the second semiconductor chip after the step of bonding the second semiconductor.
In accordance with another embodiment of the present invention, there is provided a method for fabricating a semiconductor package, comprising: providing a circuit board, the circuit board having a resin layer and two circuit patterns, the resin layer being provided with an opening at its center portion, the circuit patterns being formed on the upper and lower surfaces of the resin layer and including a plurality of bond fingers and ball lands exposed to the outside, wherein the circuit patterns are connected to each other through one or more via holes; bonding at least one semiconductor chip over the opening of the circuit board, and connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board with connection means; primarily encapsulating the upper surface of the opening of the circuit board and the semiconductor chip with an encapsulating material; disposing at least one semiconductor chip, on the lower surface of which a plurality of input/output pads are formed, within the opening of the circuit board, and connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board with connection means; secondly encapsulating a predetermined area of the lower surface of the circuit board covering the semiconductor chip and the opening with an encapsulating material; and fusion-bonding a plurality of conductive balls on the ball lands of the circuit board.